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Conference Proceedings

Gulur, Nagendra and Mehendale, Mahesh and Manikantan, R and Govindarajan, R (2014) Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. In: 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), DEC 13-17, 2014, Cambridge, ENGLAND, pp. 38-50.

Manikantan, R and Rajan, Kaushik and Govindarajan, R (2012) Probabilistic Shared Cache Management (PriSM). In: 39th Annual International Symposium on Computer Architecture (ISCA), JUN 09-13, 2012 , Portland, OR, USA, pp. 428-439.

Manikantan, R and Govindarajan, R and Rajan, Kaushik (2011) Extended histories: improving regularity and performance in correlation prefetchers. In: HiPEAC '11 Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, 2011, New York, NY, USA.

Conference Paper

Gulur, Nagendra Dwarakanath and Manikantan, R and Mehendale, Mahesh and Govindarajan, R (2012) Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. In: ICS '12 Proceedings of the 26th ACM International Conference on Supercomputing, 2012, New York, NY, USA.

Manikantan, R and Rajan, Kaushik and Govindarajan, Ramaswamy (2011) NUcache: an efficient multicore cache organization based on next-use distance. In: 2011 IEEE 17th International Symposium on High Performance Computer Architecture (HPCA), 12-16 Feb. 2011, San Antonio, TX.

Gulur, Nagendra and Manikantan, R and Govindarajan, Ramaswamy and Mehendale, Mahesh M (2011) Row-buffer reorganization: simultaneously improving performance and reducing energy in DRAMs. In: 2011 International Conference on Parallel Architectures and Compilation Techniques (PACT), 10-14 Oct. 2011, Galveston, TX.

Manikantan, R and Rajan, Kaushik and Govindarajan, R (2010) NUcache: A Multicore Cache Organization Based on Next-Use Distance. In: 19th International Conference on Parallel Architectures and Compilation Techniques, SEP 11-15, 2010, Austrian Acad Sci Vienna, Vienna, AUSTRIA, pp. 569-570.