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Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth

Gulur, Nagendra and Mehendale, Mahesh and Manikantan, R and Govindarajan, R (2014) Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. In: 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), DEC 13-17, 2014, Cambridge, ENGLAND, pp. 38-50.

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Official URL: http://dx.doi.org/10.1016/j.amc.2015.09.086


In this paper, we present Bi-Modal Cache - a flexible stacked DRAM cache organization which simultaneously achieves several objectives: (i) improved cache hit ratio, (ii) moving the tag storage overhead to DRAM, (iii) lower cache hit latency than tags-in-SRAM, and (iv) reduction in off-chip bandwidth wastage. The Bi-Modal Cache addresses the miss rate versus off-chip bandwidth dilemma by organizing the data in a bi-modal fashion - blocks with high spatial locality are organized as large blocks and those with little spatial locality as small blocks. By adaptively selecting the right granularity of storage for individual blocks at run-time, the proposed DRAM cache organization is able to make judicious use of the available DRAM cache capacity as well as reduce the off-chip memory bandwidth consumption. The Bi-Modal Cache improves cache hit latency despite moving the metadata to DRAM by means of a small SRAM based Way Locator. Further by leveraging the tremendous internal bandwidth and capacity that stacked DRAM organizations provide, the Bi-Modal Cache enables efficient concurrent accesses to tags and data to reduce hit time. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement (in terms of Average Normalized Turnaround Time (ANTT)) of 10.8%, 13.8% and 14.0% in 4-core, 8-core and 16-core workloads respectively.

Item Type: Conference Proceedings
Series.: International Symposium on Microarchitecture Proceedings
Publisher: IEEE
Additional Information: Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre: Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 02 Jan 2016 10:21
Last Modified: 02 Jan 2016 10:21
URI: http://eprints.iisc.ac.in/id/eprint/53026

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