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Shayan, Md and Singh, Virendra and Singh, Adit D and Fujita, Masahiro (2012) SEU Tolerant Robust Memory Cell Design. In: IEEE 18th International On-Line Testing Symposium (IOLTS), JUN 27-29, 2012, Sitges, SPAIN, pp. 13-18.
Adiga, Raghavendra and Arpit, Gandhi and Singh, Virendra and Saluja, Kewal K and Fujiwara, Hideo and Singh, Adit D (2010) On Minimization of Test Application Time for RAS. In: 23rd International Conference on VLSI Design/9th International Conference on Embedded Systems, JAN 03-07, 2010, Bangalore, India, pp. 393-398.
Abhishek, A and Khan, Amanulla and Singh, Virendra and Saluja, Kewal K and Singh, Adit D (2010) Test Application Time Minimization for RAS using Basis Optimization of Column Decoder. In: International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), MAY 30-JUN 02, 2010, Paris, FRANCE, pp. 2614-2617.
Deepak, KG and Reyna, Robinson and Singh, Virendra and Singh, Adit D (2009) Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. In: 18th Asian Test Symposium, NOV 23-26, 2009, Taichung.
