ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing

Deepak, KG and Reyna, Robinson and Singh, Virendra and Singh, Adit D (2009) Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. In: 18th Asian Test Symposium, NOV 23-26, 2009, Taichung.

[img] PDF
getPDF.pdf_4.pdf - Published Version
Restricted to Registered users only

Download (386kB) | Request a copy
Official URL: http://ieeexplore.ieee.org/search/srchabstract.jsp...


Enhanced Scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial Enhanced Scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS'89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: copyright of this article belongs to IEEE
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited: 26 Mar 2010 11:40
Last Modified: 18 Oct 2011 07:11
URI: http://eprints.iisc.ac.in/id/eprint/26560

Actions (login required)

View Item View Item