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SEU Tolerant Robust Memory Cell Design

Shayan, Md and Singh, Virendra and Singh, Adit D and Fujita, Masahiro (2012) SEU Tolerant Robust Memory Cell Design. In: IEEE 18th International On-Line Testing Symposium (IOLTS), JUN 27-29, 2012, Sitges, SPAIN, pp. 13-18.

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Official URL: http://dx.doi.org/10.1109/IOLTS.2012.6313834


The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Q(crit) of a standard 6T SRAM cell.

Item Type: Conference Paper
Series.: IEEE International On-Line Testing Symposium
Publisher: IEEE
Additional Information: Copyright for this article belongs to IEEE, NEW YORK,
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 07 Feb 2013 11:50
Last Modified: 07 Feb 2013 11:50
URI: http://eprints.iisc.ac.in/id/eprint/45750

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