|
 | Up a level |
Madhu, Kavitha T and Das, Saptarsi and Nalesh, S and Nandy, SK and Narayan, Ranjani (2015) Compiling HPC Kernels for the REDEFINE CGRA. In: 2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC), AUG 24-26, 2016, Int Symposium Cyberspace Safety & Secur, New York, NY, pp. 405-410.
Nalesh, S and Madhu, Kavitha T and Das, Saptarsi and Nandy, SK and Narayan, Ranjani (2015) Energy Aware Synthesis of Application Kernels expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. In: IEEE International Symposium on Nanoelectronic and Information Systems, DEC 21-23, 2015, Indore, INDIA, pp. 7-12.
Mahapatra, Ipsita Biswas and Natarajan, Santhi and Nalesh, S and Nandy, SK (2015) SIMAAH: RTL simulation accelerator for complex SoC's. In: IEEE International Conference on Electronics Computing and Communication Technologies (CONECCT), JUL 10-11, 2015, JUL 10-11, 2015.
Madhu, Kavitha T and Das, Saptarsi and Krishna, Madhava C and Nalesh, S and Nandy, SK and Narayan, Ranjani (2014) Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 215-224.
Kala, S and Nalesh, S and Nandy, SK and Narayan, Ranjani (2013) Design of a Low Power 64 Point FFT Architecture for WLAN Applications. In: 25th International Conference on Microelectronics (ICM), DEC 15-18, 2013, Beirut, LEBANON.
Kala, S and Nalesh, S and Maity, Arka and Nandy, SK and Narayan, Ranjani (2013) High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit. In: IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-23, 2013, Beijing, PEOPLES R CHINA, pp. 3034-3037.
Kala, S and Nalesh, S and Jose, BR and Mathew, J and Ottavi, M (2018) Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. In: 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018, 10 - 12 April 2018, Taormina, pp. 1-2.
Merchant, Farhad and Maity, Arka and Mahadurkar, Mahesh and Vatwani, Kapil and Munje, Ishan and Krishna, Madhava and Nalesh, S and Gopalan, Nandhini and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2015) Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 153-158.
Mohammadi, Mahnaz and Krishna, Akhil and Nalesh, S and Nandy, S K (2018) A Hardware Architecture for Radial Basis Function Neural Network Classifier. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 29 (3). pp. 481-495.
Nalesh, S and Madhu, Kavitha T and Das, Saptarsi and Nandy, S K and Narayan, Ranjani (2017) Energy aware synthesis of application kernels through composition of data-paths on a CGRA. In: INTEGRATION-THE VLSI JOURNAL, 58 . pp. 320-328.
