High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit

Kala, S and Nalesh, S and Maity, Arka and Nandy, SK and Narayan, Ranjani (2013) High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit. In: IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-23, 2013, Beijing, PEOPLES R CHINA, pp. 3034-3037.

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Abstract

In this paper we propose a fully parallel 64K point radix-4(4) FFT processor. The radix-4(4) parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. The radix-4(4) block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. The resultant 64K point FFT processor shows significant reduction in intermediate memory but with increased hardware complexity. Compared to the state-of-art implementation 5], our architecture shows reduced latency with comparable throughput and area. The 64K point FFT architecture was synthesized using a 130nm CMOS technology which resulted in a throughput of 1.4 GSPS and latency of 47.7 mu s with a maximum clock frequency of 350MHz. When compared to 5], the latency is reduced by 303 mu s with 50.8% reduction in area.

Item Type:	Conference Proceedings
Series.:	IEEE International Symposium on Circuits and Systems
Publisher:	IEEE
Additional Information:	copyright for this article belongs to IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	03 Jun 2014 08:26
Last Modified:	03 Jun 2014 08:26
URI:	http://eprints.iisc.ac.in/id/eprint/49086

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