Design of a Low Power 64 Point FFT Architecture for WLAN Applications

Kala, S and Nalesh, S and Nandy, SK and Narayan, Ranjani (2013) Design of a Low Power 64 Point FFT Architecture for WLAN Applications. In: 25th International Conference on Microelectronics (ICM), DEC 15-18, 2013, Beirut, LEBANON.

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Abstract

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

Item Type:	Conference Proceedings
Series.:	International Conference on Microelectronics-ICM
Publisher:	IEEE
Additional Information:	copyright for this article belongs to IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Keywords:	Fast Fourier Transform; Radix-4(3); VLSI
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	03 Jun 2014 08:25
Last Modified:	03 Jun 2014 08:25
URI:	http://eprints.iisc.ac.in/id/eprint/49085

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