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Srinivasaiah, HC and Bhat, Navakanta (2004) Response Surface Modeling of 100 nm CMOS Process Technology using Design of Experiment. In: 17th International Conference on VLSI Design, 2004, 5-9 January, Mumbai,India, 285 -290.
Srinivasaiah, HC and Bhat, Navakanta (2002) Implant Dose Sensitivity of $0.1\hspace{5mm}{\mu}m$ CMOS Inverter Delay. In: 7th Asia and South Pacific Design Automation Conference 15th International Conference on VLSI Design, 2002. ASP-DAC 2002, 7-11 January, Bangalore,India, 225 -230.
Srinivasaiah, HC and Bhat, Navakanta (2005) Characterization of sub-100nm CMOS process using screening experiment technique. In: Solid-State Electronics, 49 (3). pp. 431-436.
Srinivasaiah, HC and Bhat, Navakanta (2003) Monte Carlo analysis of the implant dose sensitivity in 0.1 &#u00B5;m NMOSFET. In: Solid-State Electronics, 47 (8). pp. 1379-1383.
Srinivasaiah, HC and Bhat, Navakanta (2003) Mixed-Mode Simulation Approach to Characterize the Circuit Delay Sensitivity to Implant Dose Variations. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22 (6). 742 -747.
