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Conference Proceedings

Ahlawat, Satyadev and Vaghani, Darshit and Tudu, Jaynarayan and Suhag, Ashok (2017) A Cost Effective Technique for Diagnosis of Scan Chain Faults. In: 21st International Symposium on VLSI Design and Test (VDAT), JUN 29-JUL 02, 2017, Indian Inst Technol Roorkee, Roorkee, INDIA, pp. 191-204.

Conference Paper

Tudu, Jaynarayan T and Ahlawat, Satyadev (2017) Guided shifting of test pattern to minimize test time in serial scan. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.

Ahlawat, Satyadev and Tudu, Jaynarayan T (2016) On minimization of test power through modified scan flip-flop. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2016) A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test. In: 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), JUL 04-06, 2016, Catalunya, SPAIN, pp. 233-238.

Ahlawat, Satyadev and Tudu, Jaynarayan and Matrosova, Anzhela and Singh, Virendra (2015) A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. In: 24th IEEE Asian Test Symposium, NOV 22-25, 2015, Mumbai, INDIA, pp. 25-30.