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On minimization of test power through modified scan flip-flop

Ahlawat, Satyadev and Tudu, Jaynarayan T (2016) On minimization of test power through modified scan flip-flop. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.

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Official URL: https://doi.org/10.1109/ISVDAT.2016.8064878


Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified scan flip-flop design which uses a low cost dynamic slave latch to shift the test vectors and allows the static slave latch to retain the responses from the previous test vector. Through bypassing the slave latch during loading/unloading operation the proposed design eliminates redundant switching activity in combinational logic and hence minimizes test power. Furthermore the proposed scan flip flop design does not use any gating element in functional path, and hence the functional performance overhead is comparatively very less than the previously proposed output gating techniques so far.

Item Type: Conference Paper
Publisher: Institute of Electrical and Electronics Engineers Inc.
Additional Information: The Copyright of this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords: Electric losses; Scanning; VLSI circuits; Combinational logic; Functional operation; Functional performance; Gating techniques; High complexity; Scan flip-flops; Switching activities; Test vectors; Flip flop circuits
Department/Centre: Division of Electrical Sciences > Computer Science & Automation
Date Deposited: 13 Jun 2022 04:48
Last Modified: 13 Jun 2022 04:48
URI: https://eprints.iisc.ac.in/id/eprint/73278

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