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Conference Paper

Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power during SoC Test. In: IEEE European Test Symposium (ETS) , May 2009.

Sindia, Suraj and Singh, Virendra and Agrawal, Vishwani D (2009) Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits. In: 18th IEEE North Atlantic Test Workshop (NATW) , May 2009, Boxborough, MA, USA.

Sindia, Suraj and Singh, Virendra and Agrawal, Vishwani D (2009) Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients. In: 18th Asian Test Symposium, NOV 23-26, 2009, Taichung.

Tudu, Jaynarayan T and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power for Scan Circuit during Test. In: 14th IEEE European Test Symposium (EST 2009), May 25-29, 2009, Seville, SPAIN, pp. 25-30.

Jacob, James and Sivakumar, PS and Agrawal, Vishwani D (1997) Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. In: Tenth International Conference on VLSI Design, 1997, 4-7 January, Hyderabad,India, 514 -515.

Majhi, Ananta K and Jacob, James and Patnaik, Lalit M and Agrawal, Vishwani D (1996) On Test Coverage of Path Delay Faults. In: Ninth International Conference on VLSI Design, 1996, 3-6 January, Bangalore,India, 418 -421.

Majhi, Ananta K and James, Jacob and Patnaik, Lalit M and Agrawal, Vishwani D (1995) An Efficient Automatic Test Generation System for Path Delay Faults in Combinational Circuits. In: 8th International Conference on VLSI Design, 4-7 January 1995, New Delhi, India, pp. 161-165.

Srinivas, MK and Jacob, James and Agrawal, Vishwani D (1995) Functional Test Generation for Non-Scan Sequential Circuits. In: 8th International Conference on VLSI Design, 1995, 4-7 January 1995, New Delhi, India, pp. 47-52.

Srinivas, MK and Jacob, James and Agrawal, Vishwani D (1992) Finite State Machine Testing Based on Growth and Disappearance Faults. In: Twenty-Second International Symposium on Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers, 8-10 July, Boston,MA, 238 -245.

Journal Article

Majhi, Ananta K and Agrawal, Vishwani D and Jacob, James and Patnaik, Lalit M (2000) Line coverage of path delay faults. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8 (5). pp. 610-614.

Srinivas, MK and Jacob, James and Agrawal, Vishwani D (1996) Functional Test Generation for Synchronous Sequential Circuits. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15 (7). 831 -843.