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Functional Test Generation for Synchronous Sequential Circuits

Srinivas, MK and Jacob, James and Agrawal, Vishwani D (1996) Functional Test Generation for Synchronous Sequential Circuits. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15 (7). 831 -843.


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We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLAs are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark PSM's from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS'89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests.

Item Type: Journal Article
Publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Publisher: IEEE
Additional Information: Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:26
URI: http://eprints.iisc.ac.in/id/eprint/6554

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