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Tudu, Jaynarayan T and Ahlawat, Satyadev (2017) Guided shifting of test pattern to minimize test time in serial scan. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.
Ahlawat, Satyadev and Tudu, Jaynarayan T (2016) On minimization of test power through modified scan flip-flop. In: 20th International Symposium on VLSI Design and Test, VDAT 2016, 24-27 May 2016, Guwahati, India, pp. 1-6.
Tudu, Jaynarayan T and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani D (2009) On Minimization of Peak Power for Scan Circuit during Test. In: 14th IEEE European Test Symposium (EST 2009), May 25-29, 2009, Seville, SPAIN, pp. 25-30.
