Extremely Large Breakdown to Snapback Voltage Offset (V_t1 > > V_BD): Another Way to Improve ESD Resilience of LDMOS Devices

Mishra, A and Kumar, BS and Monishmurali, M and Suzaad, SA and Kumar, S and Sanjay, KP and Singh, AK and Gupta, A and Shrivastava, M (2023) Extremely Large Breakdown to Snapback Voltage Offset (V_t1 > > V_BD): Another Way to Improve ESD Resilience of LDMOS Devices. In: 61st IEEE International Reliability Physics Symposium, IRPS 2023, 26-30 March 2023, Monterey.

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Abstract

Extremely large snapback voltage as an alternate way to improve the ESD robustness is proposed for the RESURF LDMOS devices which usually have low failure threshold. Vt1 >> VBD is a 'fail-to-protect' condition of the device which enables ESD protection to high-voltage power pins, expanding the ESD protection window for I/O applications. RESURF-implants in LDMOS result in lower It1, which is favorable for I/O devices with lower leakage. The effect of different LDMOS design approaches, load lines, and ESD stress duration on the Vt1 is systematically evaluated, using TLP experiments and 3D TCAD simulations. Finally, device design engineering guidelines are presented to achieve large Vt1, while developing physical insights into the underlying mechanisms

Item Type:	Conference Paper
Publication:	IEEE International Reliability Physics Symposium Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Breakdown Voltage; Electrostatic Discharge (ESD); Laterally Double Diffused MOS (LDMOS); Reduced Surface Field (RESURF); Snapback Voltage
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	07 Jul 2023 07:22
Last Modified:	07 Jul 2023 07:22
URI:	https://eprints.iisc.ac.in/id/eprint/82109

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