A Novel High performance D-latch using Gate Engineered Schottky device

Mir, MA and Loan, SA (2022) A Novel High performance D-latch using Gate Engineered Schottky device. In: 5th International Conference on Multimedia, Signal Processing and Communication Technologies, IMPACT 2022, 26 - 27 November 2022, Aligarh.

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Abstract

In this paper, we propose and simulate a novel D latch design employing a metal silicide source/drain Schottky structure based Sajad Sunil Schottky (SSS) device. The technology is utilised in the realisation of D latch using split gate technique. Conventional D-latch employs at least 4 NAND gates i.e. 16 MOS transistors for its CMOS implementation which therefore calls for more area as well as consumes more power. The novelty of our design is that it reduces the transistor count that is as low as 3 and thereby enhances the packaging density along with retaining all the benefits of the parent device like elimination of series resistance problem, Low power dissipation, reduced number of junctions and reduction in thermal budget due to inclusion of metal source/drain. © 2022 IEEE.

Item Type:	Conference Paper
Publication:	2022 5th International Conference on Multimedia, Signal Processing and Communication Technologies, IMPACT 2022
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copy rights of the article belong to Institute of Electrical and Electronics Engineers Inc.
Keywords:	Electric resistance; Schottky barrier diodes; Silicides; D-latch; Leakage; Metal silicide; Performance; Propagation delays; Sajad sunil schottky device; Schottky barriers; Schottky devices; Schottky structures; Silicide source/drain; Budget control
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	14 Mar 2023 05:22
Last Modified:	14 Mar 2023 05:22
URI:	https://eprints.iisc.ac.in/id/eprint/80899

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