Lu, C and Banerjee, U and Basu, K (2022) Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic. In: Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 23 - 26 October 2022, Olympic Valley, pp. 109-116.
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Abstract
Quantum computing furnishes exponential speed up over classical computing in specific areas. For example, Shor's algorithm can factor two numbers in a polynomial time complexity. Thus, many encryption algorithms that rely on large number factorization are potentially vulnerable to quantum computers. In order to address this, the National Institute of Standard and Test (NIST) has organized a competition to evaluate several post quantum cryptography (PQC) algorithms, that are secure from the attacks from quantum computers. Several of these lattice-based PQC encryption algorithms are based on Learning With Errors (LWE) computation. Conversely, LWE is the heaviest computation in a classical computer, which incurs significant portion of the latency overhead for the entire encryption algorithm. In this paper, we design an optimized quantum circuit for LWE computation. The proposed quantum circuit does not need any ancillary qubits and scales efficiently and easily if there are more qubits available on a higher qubit quantum computer. © 2022 IEEE.
Item Type: | Conference Paper |
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Publication: | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Additional Information: | The copyright for this article belongs to Institute of Electrical and Electronics Engineers Inc. |
Keywords: | Logic circuits; Polynomial approximation; Quantum cryptography; Quantum efficiency; Quantum optics; Timing circuits, Design and analysis; Encryption algorithms; Error computation; Error matrices; Learning with error; Learning with Errors; Post quantum cryptography; Quanta computers; Quantum circuit; Quantum Computing, Qubits |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 03 Feb 2023 03:39 |
Last Modified: | 03 Feb 2023 03:39 |
URI: | https://eprints.iisc.ac.in/id/eprint/79799 |
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