A novel design of ternary level SRAM cell using CNTFET

Niranjan, S and Sandesh, S and Vasundara Patel, KS (2018) A novel design of ternary level SRAM cell using CNTFET. In: 2018 International Conference on Networking, Embedded and Wireless Systems, ICNEWS 2018, 27 - 28 December 2018, Bangalore.

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Abstract

CNTFETs present a new alternative of ternary operation against the usual binary operation of Si CMOS technology. Ternary logic offers several advantages over binary logic such as increased bit density and energy efficiency due to increased functionality possible in a given chip area. This paper presents a novel design of ternary Static Read Access Memory (SRAM) using Carbon Nano-tube Field Effect Transistors (CNTFETs). Advantages of CNTFET technology along with a brief discussion on Stanford university model of CNTFET used for simulation of SRAM are discussed. The proposed design and performance parameters such as Power, Delay, Static Noise Margin (SNM) along with circuit performance under VT variations are discussed. With a supply voltage of 0.9V, we obtained good SNM values with the use of fewer transistors along with better delay and power figures.

Item Type:	Conference Paper
Publication:	2018 International Conference on Networking, Embedded and Wireless Systems, ICNEWS 2018 - Proceedings
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	The copyright for this article belongs to the Institute of Electrical and Electronics Engineers Inc.
Keywords:	Carbon nanotube field effect transistors; Carbon nanotubes; Computer circuits; Delay circuits; Embedded systems; Energy efficiency; Integrated circuit design; Logic design, Butterfly Diagram; CNTFETs; Memory design; PVT variations; SRAM design; Ternary logic, Static random access storage
Department/Centre:	Division of Interdisciplinary Sciences > Centre for Nano Science and Engineering
Date Deposited:	01 Aug 2022 09:10
Last Modified:	01 Aug 2022 09:10
URI:	https://eprints.iisc.ac.in/id/eprint/75101

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