Kumar, V and Saravanan, GS and Duraiswamy, P and Selvaraja, SK (2021) Single Stage Low Noise Inductor-Less TIA for RF over Fiber Communication. In: IEEE Access, 9 . pp. 141504-141512.
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Abstract
This paper presents design, mathematical analysis, and measurement of low noise single-stage transimpedance amplifier (TIA) with scalable bandwidth using 130 nm bipolar complementary metal-oxide-semiconductor (BiCMOS) silicon-germanium (SiGe) process. Common-emitter (CE) shunt-shunt feedback topology with active inductor peaking has been used in the design for improving noise, gain and driving capability of TIA by decreasing the input and output impedance, respectively. The use of active inductive peaking in CE shunt-shunt feedback topology has resulted in a new TIA configuration with better performance. The circuit has been optimized for low noise by adopting the proposed design technique. Validity of the mathematical analysis and design for the proposed TIA has been established with the help of simulations as well as measurement results. The measurement results of Ku-band TIA (10 MHz to 14 GHz) have demonstrated a transimpedance gain of $53.2~dB\Omega $ , input-referred current noise of 16.8 pA/ $\sqrt {Hz}$ with power consumption of $9.8~~mW $. The design architecture is adaptable for higher frequency bands, which has been demonstrated by designing another TIA covering K- and Ka-bands (10 MHz to 35 GHz) with transimpedance gain of 33.4 dB $\Omega $ , input-referred current noise of 29.4 pA/ $\sqrt {Hz}$ with power consumption of $28.1~~mW $ in the post-layout simulation results, and occupies same chip area as that of 14 GHz, i.e., $0.1\times 0.21\,\,mm^{2}$
| Item Type: | Journal Article |
|---|---|
| Publication: | IEEE Access |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Additional Information: | The copyright for this article belongs to the Authors. |
| Keywords: | Bandwidth; BiCMOS technology; Bismuth alloys; Circuit simulation; Electric inductors; Electric power utilization; Feedback amplifiers; Integrated circuit design; Metals; MOS devices; Operational amplifiers; Oxide semiconductors; Si-Ge alloys; Silicon photonics; Timing circuits, Active inductors; Bipolar complementary metal-oxide-semiconductor; Common emitter topology; Gain; Inductive peaking; Integrated circuit modeling; Lower noise; Performances evaluation; Resistance; Single stage, Topology |
| Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
| Date Deposited: | 06 Jun 2023 10:07 |
| Last Modified: | 06 Jun 2023 10:07 |
| URI: | https://eprints.iisc.ac.in/id/eprint/81813 |
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