Nair, AR and Chakrabartty, S and Thakur, CS (2022) In-Filter Computing for Designing Ultralight Acoustic Pattern Recognizers. In: IEEE Internet of Things Journal, 9 (8). pp. 6095-6106.
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Abstract
We present a novel in-filter computing framework that can be used for designing ultralight acoustic classifiers for use in the smart Internet of Things (IoT). Unlike a conventional acoustic pattern recognizer, where the feature extraction and classification are designed independently, the proposed architecture integrates the convolution and nonlinear filtering operations directly into the kernels of a support vector machine (SVM). The result of this integration is a template-based SVM whose memory and computational footprint (training and inference) is light enough to be implemented on a field-programmable gate array (FPGA)-based IoT platform. While the proposed in-filter computing framework is general enough, in this article, we demonstrate this concept using a cascade of an asymmetric resonator with inner hair cells (CAR-IHCs)-based acoustic feature extraction algorithm. The complete system has been optimized using time-multiplexing and parallel-pipeline techniques for a Xilinx Spartan 7 series FPGA. We show that the system can achieve robust classification performance on benchmark sound recognition tasks using only 1.5k lookup tables (LUTs) and 2.8k flip-flops (FFs), a significant improvement over other approaches.
| Item Type: | Journal Article |
|---|---|
| Publication: | IEEE Internet of Things Journal |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Additional Information: | The copyright for this article belongs to the Authors. |
| Keywords: | Acoustic resonators; Audio acoustics; Benchmarking; Extraction; Feature extraction; Field programmable gate arrays (FPGA); Flip flop circuits; Integrated circuit design; Internet of things; Table lookup, Acoustic feature extraction; Computing frameworks; Feature extraction and classification; Filtering operations; Internet of thing (IoTs); Pattern recognizers; Proposed architectures; Robust classification, Support vector machines |
| Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
| Date Deposited: | 24 Jun 2022 11:48 |
| Last Modified: | 24 Jun 2022 11:48 |
| URI: | https://eprints.iisc.ac.in/id/eprint/73688 |
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