Sidharthan, P and Narayanan, G (2013) Reduction of Tab-to-Chassis Capacitance of a Power MOSFET and Conducted Emission through Proper Mounting Arrangement. In: National Power Electronics Conference (NPEC) 2013, 20-23 December, 2013, Indian Institute of Technology Kanpur, Kanpur, Uttar Pradesh, INDIA.
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Reduction of Tab-to-Chassis Capacitance... P. Sidharthan, G. Narayanan.pdf - Published Version Download (868kB) | Preview |
Abstract
Tab-to-chassis capacitance of a power MOSFET and associated conducted emission is a matter of growing concern for switched-mode power converters as one prefers higher switching frequency to shrink the size and tries to limit the common-mode noise as mandated by contemporary electromagnetic emission norms. This paper explores a few techniques of mounting a MOSFET to the chassis to reduce conducted common-mode emission through proper dielectric isolation and shielding mechanism without compromising the thermal management. The effects are studied using analytical approach as well as through experiments. It is found that the connection of the device lead to a copper shield sandwiched between two dielectric sheets reduces the common-mode current by as much as 20 dB.
| Item Type: | Conference Proceedings |
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| Keywords: | Common-mode interference, Electromagnetic interference, Electromagnetic compatibility, power MOSFET, switch mode power supply |
| Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
| Date Deposited: | 28 Nov 2021 09:41 |
| Last Modified: | 28 Nov 2021 09:41 |
| URI: | http://eprints.iisc.ac.in/id/eprint/70399 |
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