Roy, Tapas and Hari, Pavan Kumar VSS and Narayanan, G (2013) Study on the Effect of Dead Time and its Compensation for Bus-Clamping PWM Techniques. In: National Power Electronics Conference NPEC, 20-22 December 2013, Indian Institute of Technology Kanpur, Kanpur, India.
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Abstract
Dead-time is provided in between the gating signals of the top and bottom semiconductor switches in an inverter leg to prevent the shorting of DC bus. Due to this dead time, there is a significant unwanted change in the output voltage of the inverter. The effect is different for different pulse width modulation (PWM) methodologies. The effect of dead-time on the output fundamental voltage is studied theoretically as well as experimentally for bus-clamping PWM methodologies. Further, experimental observations on the effectiveness of dead-time compensation are presented.
| Item Type: | Conference Paper |
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| Publisher: | IIT Kanpur |
| Additional Information: | Copyright for this article belongs to the authors. |
| Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
| Date Deposited: | 28 Jan 2014 06:28 |
| Last Modified: | 28 Jan 2014 06:28 |
| URI: | http://eprints.iisc.ac.in/id/eprint/48292 |
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