Response Surface Modeling of 100 nm CMOS Process Technology using Design of Experiment

Srinivasaiah, HC and Bhat, Navakanta (2004) Response Surface Modeling of 100 nm CMOS Process Technology using Design of Experiment. In: 17th International Conference on VLSI Design, 2004, 5-9 January, Mumbai,India, 285 -290.

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Abstract

100 nm CMOS technology has been characterized through Design of Experiment (DOE) and statistical modeling. Initially, a set of 21 process parameters (factors) have been identified to determine their impact on transistor performance metrics such as threshold voltage $V_t$, sub-threshold slope SS, drive current $I_{ddrive}$, leakage current $I_{dleak}$, both in saturation and linear region. Through first order linear modeling of $V_t$, SS, $I_{ddrive}$, and $I_{dleak}$, a subset of 10 most significant process parameters are picked using Plackett-Burman screening experiment for both NMOS and PMOS devices. Significant process parameters which impact the device characteristics are seen to be different, for NMOS and PMOS devices, inspite of a common process flow. Response surfaces (RS) have been built in terms of these 10 parameters for NMOS device. Statistical parameters of the device characteristics fluctuations like mean$(\mu)$ and standard deviation $(\sigma)$ for $V_t$, SS, $I_{ddrive}$, $I_{dleak}$ and $G_m$ (maximum transconductance), have been determined by Monte Carlo (MC) analysis of these response surfaces. Application of the Transmission of Moment Technique (TMT) on these models is shown to be a simple means to determine $\mu$ and $\sigma$ of the device characteristics, with simple mathematical calculations.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	©1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	Disposable spacer;Sensitivity analysis;CMOS technology;Transmission of moments technique;Statistical modeling;Plackettburman design;Response surface methodology;Monte carlo analysis
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	21 Dec 2005
Last Modified:	19 Sep 2010 04:22
URI:	http://eprints.iisc.ac.in/id/eprint/4696

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