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Power optimization in current mode circuits

Bhat, MS and Jamadagni, HS (2005) Power optimization in current mode circuits. In: 18th International Conference on VLSI Design, 2005, 3-7 January, Kolkata, India, pp. 175-180.


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We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in a current comparator circuit. Power reduction is achieved through turning off the redundant comparator circuits using a switch-architecture. Simulations are carried-out for current-mode flash ADC designs and literal generating circuits for MVL. We show that the simple switch architecture with minimum area overhead can be used to trade-off power dissipation with delay in these designs.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: C 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 22 Nov 2005
Last Modified: 19 Sep 2010 04:21
URI: http://eprints.iisc.ac.in/id/eprint/4093

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