Logic Simulation Using T-Algorithm on Network of Workstations

Sundaram, S and Srinivas, MK (1994) Logic Simulation Using T-Algorithm on Network of Workstations. In: IEEE Region 10's Ninth Annual International Conference. Theme: 'Frontiers of Computer Technology'. TENCON '94, 22-26 August, Singapore, vol.1, 285-289.

Preview

PDF logic.pdf Download (338kB)

Abstract

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulation algorithms is by exploiting the inherent parallelism in the sequential version. We propose a T-algorithm based logic simulation algorithm on a network of workstations interconnected by a local area network. The main objective has been to balance the computational load among the processors and at the same time reduce the communication to a bare minimum. We have achieved these by partitioning the circuit into cones containing gates in a fanout free region (FFR). Further, the cones of FFRs at the same level (having the same distance from primary inputs) are assigned by the master processor and communicated to the other workstations through the network. We have kept the balance on the computational load among slave processors by assigning a proper number of FFR cones, using a good heuristic. We have also shown that FFR partitioning reduces the amount of communication between the processors We have implemented the distributed logic simulation algorithm on a network of workstations using the communication primitives send and receive on sockets provided by the BSD 4.2 network library. The paper concludes with a tabulated results on the timings obtained on the ISCAS[8] benchmark circuits.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	Copyright 1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords:	Logic Simulation;Distributed Processing;Network of Workstations;T-Algorithm
Department/Centre:	Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre
Date Deposited:	30 May 2006
Last Modified:	19 Sep 2010 04:27
URI:	http://eprints.iisc.ac.in/id/eprint/7137

Actions (login required)

View Item