A Cascaded Nine-Level Inverter Topology with T-Type and H-Bridge with Increased DC-Bus Utilization

Pal, S and Majumder, MG and Rakesh, R and Gopakumar, K and Umanand, L and Zielinski, D and Beig, AR (2021) A Cascaded Nine-Level Inverter Topology with T-Type and H-Bridge with Increased DC-Bus Utilization. In: IEEE Transactions on Power Electronics, 36 (1). pp. 285-294.

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Abstract

This article introduces a hybrid nine-level inverter topology with extended dc-bus utilization for operation at over modulation range without the presence of lower order harmonics (predominantly fifth and seventh) when compared to conventional two-level and multilevel inverter with hexagonal voltage space vector structure. The proposed inverter is a cascade of a five-level T-type unit and an H-bridge (HB) unit. An increase in the dc-bus utilization is possible by increasing the pole voltage levels to ± (V\textdc/2+V\textdc/8) using the HB capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned pulsewidth modulation strategy allows us to increase the peak phase fundamental voltage from 0.577V\textdc to 0.625V\textdc in case of unity power factor (p.f) load and to 0.637V\textdc for 0.82 p.f load with the proposed nine-level inverter. The limiting factor on increasing the dc bus utilization such as p.f, HB capacitor balancing are analysed broadly in this article. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype. © 1986-2012 IEEE.

Item Type:	Journal Article
Publication:	IEEE Transactions on Power Electronics
Publisher:	Institute of Electrical and Electronics Engineers Inc.
Additional Information:	cited By 0; Institute of Electrical and Electronics Engineers Inc.
Keywords:	Electric inverters; Modulation; Topology; Vector spaces, Bus utilizations; Capacitor voltages; Inverter topologies; Lower order harmonics; Multilevel inverter; Over modulation; Unity power factor; Voltage space vectors, Bridge circuits
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	20 Oct 2020 06:58
Last Modified:	20 Oct 2020 06:58
URI:	http://eprints.iisc.ac.in/id/eprint/66736

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