Kranthi, NK and Sampath Kumar, B and Salman, A and Boselli, G and Shrivastava, M (2020) Design Insights to Address Low Current ESD Failure and Power Scalability Issues in High Voltage LDMOS-SCR Devices. In: 2020 IEEE International Reliability Physics Symposium, IRPS 2020, 28 April-30 May 2020, Virtual, Online; United States.
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Abstract
Power-scalability issues for longer pulse duration discharges (PW>100ns) in high voltage LDMOS-SCR devices is evaluated. The severity of the problem with increasing LDMOS voltage classes is highlighted with a need for newer design strategies. A systematic design approach is presented to evaluate the effect of different design parameters on LDMOS filament and SCR turn-on near the snapback region. Finally design guidelines are presented to improve the power scalability without compromising on its ON-state DC (functional) and Safe Operating Area (SOA) characteristics. © 2020 IEEE.
Item Type: | Conference Paper |
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Publication: | IEEE International Reliability Physics Symposium Proceedings |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Additional Information: | cited By 0; Conference of 2020 IEEE International Reliability Physics Symposium, IRPS 2020 ; Conference Date: 28 April 2020 Through 30 May 2020; Conference Code:161550 |
Keywords: | HVDC power transmission; MOS devices; Scalability, Design insights; Design parameters; Design strategies; High voltage; Power scalability; Pulse durations; Safe operating area; Systematic design approach, Electrostatic discharge |
Department/Centre: | Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology) |
Date Deposited: | 09 Oct 2020 06:20 |
Last Modified: | 09 Oct 2020 06:20 |
URI: | http://eprints.iisc.ac.in/id/eprint/66180 |
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