Resistance Emulation based Fault Ride-Through in Standalone Voltage Source Inverters

Mallik, Rahul and Venkatramanan, D and Adapa, Anil Kumar and John, Vinod (2017) Resistance Emulation based Fault Ride-Through in Standalone Voltage Source Inverters. In: 2017 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE (ITEC-INDIA), DEC 13-15, 2017, Pune, INDIA.

PDF Iee_Tra_Ele_Conf_2017.pdf - Published Version Restricted to Registered users only Download (572kB) | Request a copy

Abstract

This paper presents a resistance emulation based fault ride through scheme for standalone voltage source inverters. Typically, fast electronic protection schemes such as overcurrent and IGBT desaturation, are employed to detect inverter overload and short-circuit faults. However, this results in complete inverter shut-down rapidly, much before the slower electromechanical protection systems such as circuit breakers can function. In this work, a resistance emulation based technique is suggested that provides fault ride-through capability to the inverter, thus allowing electromechanical protections to function. A state machine is presented which incorporates hierarchal loop stability and multiple current constraints for appropriate impedance selection. The proposed method is verified in hardware.

Item Type:	Conference Paper
Series.:	IEEE Transportation Electrification Conference and Expo
Publisher:	IEEE
Additional Information:	Copyright for this article belongs to IEEE.
Keywords:	Fault Ride Through; Impedance Emulation; Second Order Generalized Integrator; Finite State Machine; Multiloop stability analysis and design
Department/Centre:	Division of Electrical Sciences > Electrical Engineering
Date Deposited:	12 Jan 2019 15:24
Last Modified:	22 Feb 2019 09:15
URI:	http://eprints.iisc.ac.in/id/eprint/61265

Actions (login required)

View Item