A High-throughput Clock-less Architecture for Soft-output Viterbi Detection

Dey, Arnab and Jose, Sebin and Varghese, Kuruvilla and Srinivasa, Shayan Garani (2017) A High-throughput Clock-less Architecture for Soft-output Viterbi Detection. In: 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 06-09, 2017, Tufts Univ, Medford Somerville Campus, Boston, MA, pp. 779-782.

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Abstract

Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect data in the presence of inter-symbol interference (ISI) and noise. Further, soft reliability values assist in the decoding of outer codes. The state-of-the-art implementations of the Viterbi algorithm are synchronous which consider the `worst-case' propagation delays of the combinational blocks for the purpose of timing analysis. This can be avoided by using asynchronous circuits that offer `average case' latencies without a clock distribution network which is one of the most power-consuming units in the existing integrated circuits. In this paper, we present a high-throughput clock-less architecture for a soft-output Viterbi detector. In 180-nm technology node, we obtain a 66.7% reduction in the power consumption for our asynchronous design in comparison to a synchronous version of the detector with throughput requirements of the order of 1.5 Gb/s. Simulation results in 65-nm technology results in 44.2% reduction in power consumption sustaining a throughput of 2.4 Gb/s.

Item Type:	Conference Proceedings
Series.:	Midwest Symposium on Circuits and Systems Conference Proceedings
Publisher:	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Additional Information:	Copy right for the article belong to IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre:	Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited:	14 Mar 2018 17:36
Last Modified:	14 Mar 2018 17:36
URI:	http://eprints.iisc.ac.in/id/eprint/59191

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