An efficient design of serial and parallel memory using Quantum dot cellular automata

Roy, Sandip Kumar and Nalini, R and Sharan, Preeta and Srinivas, T (2015) An efficient design of serial and parallel memory using Quantum dot cellular automata. In: IEEE Region 10 Conference, NOV 01-04, 2015, Macao, PEOPLES R CHINA.

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Abstract

Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10mm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%. These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

Item Type:	Conference Proceedings
Series.:	TENCON IEEE Region 10 Conference Proceedings
Additional Information:	Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	08 Oct 2016 07:18
Last Modified:	08 Oct 2016 07:18
URI:	http://eprints.iisc.ac.in/id/eprint/54805

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