Compiling Affine Loop Nests for Distributed-Memory Parallel Architectures

Bondhugula, Uday (2013) Compiling Affine Loop Nests for Distributed-Memory Parallel Architectures. In: International Conference for High Performance Computing, Networking, Storage and Analysis (SC), NOV 17-22, 2013, Denver, CO.

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Abstract

We present new techniques for compilation of arbitrarily nested loops with affine dependences for distributed-memory parallel architectures. Our framework is implemented as a source-level transformer that uses the polyhedral model, and generates parallel code with communication expressed with the Message Passing Interface (MPI) library. Compared to all previous approaches, ours is a significant advance either (1) with respect to the generality of input code handled, or (2) efficiency of communication code, or both. We provide experimental results on a cluster of multicores demonstrating its effectiveness. In some cases, code we generate outperforms manually parallelized codes, and in another case is within 25% of it. To the best of our knowledge, this is the first work reporting end-to-end fully automatic distributed-memory parallelization and code generation for input programs and transformation techniques as general as those we allow.

Item Type:	Conference Proceedings
Series.:	International Conference for High Performance Computing Networking Storage and Analysis
Publisher:	IEEE
Additional Information:	Copy right for this article belongs to the IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Keywords:	Polyhedral model; distributed-memory; code generation; affine loop nests; parallelization
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	19 Aug 2016 09:47
Last Modified:	19 Aug 2016 09:47
URI:	http://eprints.iisc.ac.in/id/eprint/54306

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