A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs

Rajanna, Viveka Konandur and Amrutur, Bharadwaj (2016) A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 24 (5). pp. 1663-1674.

PDF IEEE_Tra_Ver_Lar_Sca_Int_Sys_24-5_1663_2016.pdf - Published Version Restricted to Registered users only Download (3MB) | Request a copy

Abstract

The most promising SRAM cells capable of operating over a wide range of supply voltages contain single-ended read ports. These systems require an external reference voltage that suitably scales to enable error-free operation of the memory, as the supply voltage is scaled. This paper presents a replica-based reference-generation technique for wide voltage range SRAMs. The proposed approach tracks the memory over the large range of supply voltages, and is tunable to extend functionality down to subthreshold voltages. In addition, a tunable delay-based timing-generation scheme is employed to enable memory functionality, in the presence of increased variation at subthreshold voltages. Configuration bits are set using a random-sampling-based Built-in Self-Test algorithm that significantly speeds up the tuning process. A 4-kb array, using the conventional 8T cell, implemented in the UMC 130-nm process, is demonstrated to function from 1.2 V down to 310 mV (at 1.3 MHz and 6.45 pJ/access). The memory consumes 0.115 pJ/bit/access at the energy optimum point of 400 mV.

Item Type:	Journal Article
Publication:	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Publisher:	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Additional Information:	Copy right for this article belongs to the IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Keywords:	Dynamic voltage scaling; internal reference generation; low-voltage SRAM; subthreshold memory; tunable delay line
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	11 Jun 2016 04:59
Last Modified:	11 Jun 2016 04:59
URI:	http://eprints.iisc.ac.in/id/eprint/53883

Actions (login required)

View Item