Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems

Viveka, KR and Amrutur, Bharadwaj (2014) Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems. In: 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014) , JAN 05-09, 2014, Mumbai, INDIA, pp. 145-149.

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Abstract

This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

Item Type:	Conference Proceedings
Series.:	International Conference on VLSI Design
Publisher:	IEEE
Additional Information:	27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), Mumbai, INDIA, JAN 05-09, 2014
Keywords:	Ultra low power; memory interface design; subthreshold; level shifter
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	21 Apr 2015 07:25
Last Modified:	21 Apr 2015 07:25
URI:	http://eprints.iisc.ac.in/id/eprint/51332

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