Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

Raghavendra, RG and Amrutur, Bharadwaj (2007) Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop. In: Glsvlsi'07: proceedings of the 2007 acm great lakes symposium on vlsi, Mar,11-13, 2007, Sigda, pp. 148-151.

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Abstract

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.

Item Type:	Conference Paper
Publisher:	Assoc computing machinery
Additional Information:	Copy rights of this article belongs to Assoc computing machinery.
Keywords:	Dual-Path Loop Filter.
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	10 Aug 2009 03:39
Last Modified:	19 Sep 2010 05:40
URI:	http://eprints.iisc.ac.in/id/eprint/22090

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