Nandy, SK and Patnaik, LM (1986) Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts. In: Computer-Aided Design, 18 (7). 380 -388.
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Abstract
An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithms for geometrical design rule verification.
| Item Type: | Journal Article |
|---|---|
| Publication: | Computer-Aided Design |
| Publisher: | Elsevier Science |
| Additional Information: | Copyright of this article belongs to Elsevier Science. |
| Keywords: | Computer-aided design;Geometrical design rule checker; Quadtrees. |
| Department/Centre: | Division of Interdisciplinary Sciences > Supercomputer Education & Research Centre |
| Date Deposited: | 04 Sep 2009 03:20 |
| Last Modified: | 19 Sep 2010 05:34 |
| URI: | http://eprints.iisc.ac.in/id/eprint/20880 |
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