Ravikanth, K and Sastry, PS and Ramakrishnan, KR and Venkatesh, YV (1988) A Reduction Architecture for the Optimal Scheduling of Binary Trees. In: Future Generation Computer Systems, 4 (3). pp. 225-233.
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Abstract
This paper addresses the problem of designing a parallel reduction architecture for applicative languages. An interconnection network that allows for scheduling of binary trees of arbitrary depth is presented. It is shown that using a static scheduling strategy the architecture achieves optimal performance while scheduling complete binary trees. Some issues related to the design of a machine based on this network are also discussed.
Item Type: | Journal Article |
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Publication: | Future Generation Computer Systems |
Publisher: | Elsevier |
Additional Information: | Copyright for this article belongs to Elsevier. |
Keywords: | reduction architecture;optimal scheduling;binary trees. |
Department/Centre: | Division of Electrical Sciences > Electrical Engineering |
Date Deposited: | 25 Aug 2008 |
Last Modified: | 19 Sep 2010 04:49 |
URI: | http://eprints.iisc.ac.in/id/eprint/15611 |
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