An Efficient Automatic Test Generation System for Path Delay Faults in Combinational Circuits

Majhi, Ananta K and James, Jacob and Patnaik, Lalit M and Agrawal, Vishwani D (1995) An Efficient Automatic Test Generation System for Path Delay Faults in Combinational Circuits. In: 8th International Conference on VLSI Design, 4-7 January 1995, New Delhi, India, pp. 161-165.

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Abstract

The new test pattern generation system for path delay faults in combinational logic circuits considers robust and nonrobust tests, simultaneously. Once a robust test is obtained for a path with a given transition, another test for the same path with the opposite transition is immediately derived with a small extra effort. To facilitate the simultaneous consideration of robust and nonrobust tests, we derive a new nine-value logic system. An efficient multiple backtrace procedure satisfies test generation objectives. We also use a path selection method which covers all lines in the logic circuit by the longest and the shortest possible paths through them. A fault simulator in the system gives information on robust and nonrobust detection of faults either from a given target set or all path faults. Experimental results on ISCAS ' 85 and ISCAS ' 89 benchmark circuits substantiate the efficiency of our algorithm in comparison to other published results.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited:	25 Aug 2008
Last Modified:	19 Sep 2010 04:37
URI:	http://eprints.iisc.ac.in/id/eprint/10838

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