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A Simple Indicator based PLL for Distorted Grid Conditions

Shan, S and Narayanan, Nakul K and Umanand, L (2018) A Simple Indicator based PLL for Distorted Grid Conditions. In: 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), 18-21 Dec. 2018, Chennai. (In Press)

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Official URL: https://doi.org/10.1109/PEDES.2018.8707667

Abstract

This paper proposes a simple indicator based phase lock loop (PLL) which is capable of producing distortionless reference waveforms in case of the presence of unbalance and harmonics in the grid. The proposed configuration also has a faster dynamic response thus catering to phase jumps as well. Unlike the existing research works, this proposal doesnt make use of filtering, signal modifications or advanced algorithms. The simplest form of synchronous reference frame (SRF) PLL is retained and effectively made use of in the simplest way to achieve the objectives. The proposed concept makes use of the idea of controlling the instantaneous acceleration between the point of common coupling (PCC) space vector and the existing d-q frame by adding the error to the PLL. This addition is activated or disabled depending on the conditions like phase jump, unbalance and harmonics leading to the acceleration. Separate algorithms indicate the condition. The proposed concept is validated with sufficient simulation results.

Item Type: Conference Proceedings
Additional Information: 8th IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Chennai, INDIA, DEC 18-21, 2018
Keywords: PLL; Grid connected converters; Unbalance; Harmonics
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Depositing User: Id for Latest eprints
Date Deposited: 20 Jun 2019 18:23
Last Modified: 26 Jun 2019 17:29
URI: http://eprints.iisc.ac.in/id/eprint/62996

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