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Conference Proceedings

Surendra, G and Banerjee, Subhasis and Nandy, SK (2003) Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation. In: Design, Automation And Test in Europe Conference And Exhibition,Proceedings, MAR 03-07, 2003, Munich, Germany.

Conference Paper

Banerjee, Subhasis and Surendra, G and Nandy, SK (2004) Exploiting Program Execution Phases to Trade Power and Performance for Media Workload. In: the ASP-DAC 2004. Asia and South Pacific Design Automation Conference, 2004, 27-30 January, Yokohama,Japan, pp. 387-389.

Surendra, G and Banerjee, Subhasis and Nandy, SK (2004) Exploiting the Behavior of Ready Instructions for Power Benefits in a Dynamically Scheduled Embedded Processor. In: The 2004 47th Midwest Symposium on Circuits and Systems, MWSCAS '04, 25-28 July, Hiroshima,Japan, Vol.2, 441 -444.

Banerjee, Subhasis and Surendra, G and Nandy, SK (2004) On the Effectiveness of Dynamically Allocating Resources Across Program Execution Phases for Media Workloads. In: The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004, 6-9 December, Tainan,Taiwan, Vol.1, 9-12.

Surendra, G and Banerjee, Subhasis and Nandy, SK (2004) Power-Performance Trade-off using Pipeline Delays. In: the ASP-DAC 2004. Asia and South Pacific Design Automation Conference, 2004, 27-30 January, Yokohama,Japan, pp. 384-386.

Surendra, G and Nandy, SK and Paul, Paul (2001) ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. In: Fourteenth International Conference on VLSI Design, 2001, 3-7 January, Bangalore,India, 85 -90.

Journal Article

Banerjee, Subhasis and Surendra, G and Nandy, SK (2008) On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. In: Journal of Systems Architecture, 54 (8). pp. 797-815.

Surendra, G and Banerjee, S and Nandy, SK (2003) On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. In: International Journal of Parallel Programming, 31 (6). pp. 469-487.