Number of items: 2.
Conference Paper
Somasekhar, Dinesh and Visvanathan, V
(1993)
A 23Q MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking.
In: Sixth International Conference on VLSI Design, 1993, 3-6 January, Bombay,India, 347 -350.
Journal Article
Somasekhar, Dinesh and Visvanathan, V
(1993)
A 230-MHz Half-Bit Level Pipelined Multiplier Using True Single-Phase Clocking.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1
(4).
pp. 415-422.
This list was generated on Thu Apr 25 17:51:25 2024 IST.
