|
 | Up a level |
Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-efficient redundant execution for chip multiprocessors. In: Proceedings of the 20th symposium on Great lakes symposium on VLSI (GLSVLSI '10), May 16-18, 2010, Brown University Campus, Providence, Rhode Island, USA.
Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K and Larsson, Erik (2010) Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding. In: IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), JUN 28-JUL 01, 2010, Chicago, IL,, pp. 121-130.
Adiga, Raghavendra and Arpit, Gandhi and Singh, Virendra and Saluja, Kewal K and Fujiwara, Hideo and Singh, Adit D (2010) On Minimization of Test Application Time for RAS. In: 23rd International Conference on VLSI Design/9th International Conference on Embedded Systems, JAN 03-07, 2010, Bangalore, India, pp. 393-398.
Abhishek, A and Khan, Amanulla and Singh, Virendra and Saluja, Kewal K and Singh, Adit D (2010) Test Application Time Minimization for RAS using Basis Optimization of Column Decoder. In: International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), MAY 30-JUN 02, 2010, Paris, FRANCE, pp. 2614-2617.
Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal K (2009) Power Efficient Redundant Execution for Chip Multiprocessor. In: Workshop on Dependable and Secure Nanocomputing (WDSN) 2009, June 2009, Lisbon, Portugal.
