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Rao, Srikanth M and Nandy, SK (2000) Controller Redesign Based Clock and Register Power Minimization. In: 2000 IEEE International Symposium on Circuits and Systems. ISCAS 2000, 28-31 May, Geneva,Switzerland, Vol.3, 275-278.
Rao, Srikanth M and Nandy, SK (2000) Power minimization using control generated clocks. In: 37th Design Automation Conference, 5-9 June, 2000, Los Angeles, USA, 794 -799.
