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Biswas, Arnab Kumar and Nandy, S K and Narayan, Ranjani (2017) Multiprocessor system-on-chip for processing data in cloud computing. [Book Chapter]
Madhu, Kavitha and Singla, Tarun and Nandy, S K and Narayan, Ranjani and Neumann, Francois and Baufreton, Philippe (2017) Work-in-Progress: REDEFINE (R)(TM) - A Case for WCET-friendly Hardware Accelerators for Real time Applications. In: International Conference on Compilers Architectures and Synthesis For Embedded Systems (CASES), OCT 15-20, 2017, Seoul, SOUTH KOREA.
Merchant, Farhad and Vatwani, Tarun and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2016) Achieving Efficient QR Factorization by Algorithm-Architecture Co-Design of Householder Transformation. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 98-103.
Merchant, Farhad and Choudhary, Nimash and Nandy, SK and Narayan, Ranjani (2016) Efficient Realization of Table Look-up based Double Precision Floating Point Arithmetic. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 415-420.
Das, Saptarsi and Sivanandan, Nalesh and Madhu, Kavitha T and Nandy, Soumitra K and Narayan, Ranjani (2016) RHyMe: REDEFINE HyperCell Multicore for Accelerating HPC Kernels. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 601-602.
Guillaumet, Tom and Sharma, Aayush and Feron, Eric and Krishna, Madhava and Narayan, Ranjani and Baufreton, Philippe and Neumann, Francois and Grolleau, Emmanuel (2016) Using Reconfigurable Multi-Core Architectures for Safety-Critical Embedded Systems. In: 35th IEEE/AIAA Digital Avionics Systems Conference (DASC), SEP 25-29, 2016, Sacramento, CA.
Madhu, Kavitha T and Das, Saptarsi and Nalesh, S and Nandy, SK and Narayan, Ranjani (2015) Compiling HPC Kernels for the REDEFINE CGRA. In: 2015 IEEE 17th International Conference on High Performance Computing and Communications (HPCC), AUG 24-26, 2016, Int Symposium Cyberspace Safety & Secur, New York, NY, pp. 405-410.
Nalesh, S and Madhu, Kavitha T and Das, Saptarsi and Nandy, SK and Narayan, Ranjani (2015) Energy Aware Synthesis of Application Kernels expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. In: IEEE International Symposium on Nanoelectronic and Information Systems, DEC 21-23, 2015, Indore, INDIA, pp. 7-12.
Biswas, Arnab Kumar and Nandy, SK and Narayan, Ranjani (2015) Network-on-Chip Router attacks and their prevention in MP-SoCs with multiple Trusted Execution Environments. In: IEEE International Conference on Electronics Computing and Communication Technologies (CONECCT), JUL 10-11, 2015, Bangalore, INDIA.
Mahadurkar, Mahesh and Merchant, Farhad and Maity, Arka and Vatwani, Kapil and Munje, Ishan and Gopalan, Nandhini and Nandy, SK and Narayan, Ranjani (2014) Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 225-232.
Merchant, Farhad and Chattopadhyay, Anupam and Garga, Ganesh and Nandy, SK and Narayan, Ranjani and Gopalan, Nandhini (2014) Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). In: 27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID), JAN 05-09, 2014, Mumbai, INDIA, pp. 258-263.
Madhu, Kavitha T and Das, Saptarsi and Krishna, Madhava C and Nalesh, S and Nandy, SK and Narayan, Ranjani (2014) Synthesis of Instruction Extensions on HyperCell, a Reconfigurable Datapath. In: International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS), JUL 14-17, 2014, Samos, GREECE, pp. 215-224.
Kala, S and Nalesh, S and Nandy, SK and Narayan, Ranjani (2013) Design of a Low Power 64 Point FFT Architecture for WLAN Applications. In: 25th International Conference on Microelectronics (ICM), DEC 15-18, 2013, Beirut, LEBANON.
Kala, S and Nalesh, S and Maity, Arka and Nandy, SK and Narayan, Ranjani (2013) High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit. In: IEEE International Symposium on Circuits and Systems (ISCAS), MAY 19-23, 2013, Beijing, PEOPLES R CHINA, pp. 3034-3037.
Das, Saptarsi and Narayan, Ranjani and Narayan, Soumitra Kumar (2012) Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields. In: 8th International Joint Conference on e-Business and Telecommunications, JUL 18-21, 2011, Seville, SPAIN , pp. 249-263.
Das, Saptarsi and Varadarajan, Keshavan and Garga, Ganesh and Mondal, Rajdeep and Narayan, Ranjani and Nandy, SK (2011) A method for flexible reduction over binary fields using a field multiplier. In: SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, 18-21 July, Seville, Spain.
Sutter, Louis and Khamvilai, Thanakorn and Monmousseau, Philippe and Mains, John B and Feron, Eric and Baufreton, Philippe and Neumann, Francois and Krishna, Madhava and Nandy, SK and Narayan, Ranjani and Haldar, Chandan (2018) Experimental Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architecture. In: IEEE/AIAA 37th Digital Avionics Systems Conference (DASC), SEP 23-27, 2018, London, ENGLAND, pp. 833-842.
Guillaumet, Tom and Feron, Eric and Baufreton, Philippe and Neumann, Francois and Madhu, Kavitha and Krishna, Madhava and Nandy, SK and Narayan, Ranjani and Haldar, Chandan (2017) Task Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architectures. In: 2017 IEEE/AIAA 36TH DIGITAL AVIONICS SYSTEMS CONFERENCE (DASC) , SEP 17-21, 2017, St Petersburg, FL.
Mohammadi, Mahnaz and Satpute, Nitin and Ronge, Rohit and Chandiramani, Jayesh Ramesh and Nandy, SK and Raihan, Aamir and Verma, Tanmay and Narayan, Ranjani and Bhattacharya, Sukumar (2015) A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 505-510.
Mahale, Gopinath and Mahale, Hamsika and Goel, Arnav and Nandy, SK and Bhattacharya, S and Narayan, Ranjani (2015) Hardware Solution For Real-time Face Recognition. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 81-86.
Merchant, Farhad and Maity, Arka and Mahadurkar, Mahesh and Vatwani, Kapil and Munje, Ishan and Krishna, Madhava and Nalesh, S and Gopalan, Nandhini and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2015) Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. In: 28th International Conference on VLSI Design (VLSID) / 14th International Conference on Embedded Systems, JAN 03-07, 2015, Bangalore, INDIA, pp. 153-158.
Fell, Alexander and Biswas, Prasenjit and Chetia, Jugantor and Nandy, SK and Narayan, Ranjani (2009) Generic Routing Rules and a Scalable Access Enhancement for the Network-on-Chip RECONNECT. In: IEEE International SOC Conference, SEP 09-11, 2009, Belfast, pp. 251-254.
Rao, Adarsha and Alle, Mythri and Sainath, V and Shaik, Reyaz and Chowhan, Rajashekhar and Sankaraiah, S and Mantha, Sravanthi and Nandy, SK and Narayan, Ranjani (2009) An Input Triggered Polymorphic ASIC for H.264 Decoding. In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 07-09, 2009, Boston, MA, USA, pp. 106-113.
Fell, Alexander and Alle, Mythri and Varadarajan, Keshavan and Biswas, Prasenjit and Das, Saptarsi and Chetia, Jugantor and Nandy, SK and Narayan, Ranjani (2009) Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration. In: proceedings of the 2009 International Conference on Compilers,Architecture and Synthesis for Embedded Systems (CASES 2009),, Grenoble,Frane.
Rao, Adrsha and Mythri, * and Nandy, SK and Narayan, Ranjani (2008) Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 02-04, 2008, Leuven.
Satrawala, AN and Varadarajan, Keshavan and Alle, Mythri and Nandy, SK and Narayan, Ranjani (2007) REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. In: Proceedings of the International Conference on Field Programmable Logic and Applications, FPL 2007, Amsterdam, Aug 2007., 27-29 Aug. 2007 , Amsterdam .
Lakshmi, J and Nandy, SK and Narayan, Ranjani and Varadarajan, Keshavan (2006) Framework for enabling highly available distributed applications for utility computing. In: 4th International Symposium on Parallel and Distributed Processing and Applications,, Dec 04-06, 2006, Sorrento, Italy, pp. 549-560.
Nainwal, KC and Lakshmi, J and Nandy, SK and Narayan, Ranjani and Varadarajan, K (2005) A Framework for QoS Adaptive Grid Meta Scheduling. In: Sixteenth International Workshop on : Database and Expert Systems Applications, 2005, 22-26 August, Denmark, pp. 292-296.
Narayan, Ranjani and Rajaraman, V (1989) A Method to Evaluate the Performance of a Multiprocessor Machine based on Data Flow Principles. In: Fourth IEEE Region 10 International Conference,TENCON '89, 22-24 November, Bombay,India, pp. 209-212.
Merchant, Farhad and Vatwani, Tarun and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, S K and Narayan, Ranjani (2018) Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 29 (8). pp. 1707-1720.
Merchant, Farhad and Chattopadhyay, Anupam and Raha, Soumyendu and Nandy, SK and Narayan, Ranjani (2017) Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. In: Parallel Processing Letters, 27 (3-4). ISSN 0129-6264
Nalesh, S and Madhu, Kavitha T and Das, Saptarsi and Nandy, S K and Narayan, Ranjani (2017) Energy aware synthesis of application kernels through composition of data-paths on a CGRA. In: INTEGRATION-THE VLSI JOURNAL, 58 . pp. 320-328.
Mahale, Gopinath and Mahale, Hamsika and Nandy, SK and Narayan, Ranjani (2016) REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. In: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 27 (12). pp. 3602-3616.
Biswas, Arnab Kumar and Nandy, SK and Narayan, Ranjani (2015) Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. In: CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 34 (10). pp. 3241-3290.
Das, Saptarsi and Madhu, Kavitha and Krishna, Madhav and Sivanandan, Nalesh and Merchant, Farhad and Natarajan, Santhi and Biswas, Ipsita and Pulli, Adithya and Nandy, SK and Narayan, Ranjani (2014) A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. In: JOURNAL OF SYSTEMS ARCHITECTURE, 60 (7). pp. 592-614.
Garga, Ganesh and Das, Saptarsi and Nandy, SK and Narayan, Ranjani and Haldar, Chandan and Jagtap, Maheshkumar P and Dash, Siba Prasad (2012) A Flexible Crypto-system Based upon the REDEFINE Polymorphic ASIC Architecture. In: Defence Science Journal, 62 (1). pp. 25-31.
Alle, Mythri and Varadarajan, Keshavan and Fell, Alexander and Reddy, Ramesh C and Joseph, Nimmy and Das, Saptarsi and Biswas, Prasenjit and Chetia, Jugantor and Rao, Adarsh and Nandy, SK and Narayan, Ranjani (2009) Redefine: Runtime Reconfigurable Polymorphic ASIC. In: ACM Transactions in Embedded Computing Systems (TECS), 9 (2).
Narayan, Ranjani and Rajaraman, V (1990) Performance analysis of a multiprocessor machine based on data flow principles. In: Microprocessing and Microprogramming, 30 (1-5). pp. 601-608.
