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Kumar, Santhosh V and Thazhuthaveetil, MJ and Govindarajan, R (2005) Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. [Book Chapter]
Gulur, Nagendra and Govindarajan, R and Mehendale, Mahesh (2016) MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. In: International Symposium on Memory Systems (MEMSYS), OCT 03-06, 2016, Washington, DC, pp. 350-361.
Nagaraj, Vaivaswatha and Govindarajan, R (2015) Approximating Flow-Sensitive Pointer Analysis Using Frequent Itemset Mining. In: Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), FEB 07-11, 2015, San Francisco, CA, pp. 225-234.
Anantpur, Jayvant and Govindarajan, R (2015) PRO: Progress Aware GPU Warp Scheduling Algorithm. In: 29th IEEE International Parallel and Distributed Processing Symposium (IPDPS), MAY 25-29, 2015, Hyderabad, INDIA, pp. 979-988.
Anantpur, Jayvant and Govindarajan, R (2015) Taming Control Divergence in GPUs through Control Flow Linearization. In: 23rd International Conference on Compiler Construction (CC), APR 05-13, 2014, Grenoble, FRANCE, pp. 133-153.
Gulur, Nagendra and Mehendale, Mahesh and Manikantan, R and Govindarajan, R (2014) Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. In: 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), DEC 13-17, 2014, Cambridge, ENGLAND, pp. 38-50.
Pai, Sreepathi and Thazhuthaveetil, Matthew J and Govindarajan, R (2013) Improving GPGPU Concurrency with Elastic Kernels. In: Eighteenth international conference on Architectural support for programming languages and operating systems , 16-20 March 2013, Houston, Texas, USA, pp. 407-418.
Nagaraj, Vaivaswatha and Govindarajan, R (2013) Parallel Flow-Sensitive Pointer Analysis by Graph-Rewriting. In: 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), SEP 07-11, 2013, Edinburgh, SCOTLAND, pp. 19-28.
Manikantan, R and Rajan, Kaushik and Govindarajan, R (2012) Probabilistic Shared Cache Management (PriSM). In: 39th Annual International Symposium on Computer Architecture (ISCA), JUN 09-13, 2012 , Portland, OR, USA, pp. 428-439.
Prasad, Ashwin and Anantpur, Jayvant and Govindarajan, R (2011) Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors. In: Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, June 4-8, 2011, San Jose, California, USA.
Manikantan, R and Govindarajan, R and Rajan, Kaushik (2011) Extended histories: improving regularity and performance in correlation prefetchers. In: HiPEAC '11 Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, 2011, New York, NY, USA.
Gajjar, Mrugesh R and Sreenivas, TV and Govindarajan, R (2011) Fast acoustic likelihood computation using low-rank matrix approximation. In: 2011 IEEE Workshop on Signal Processing Systems, October 4-7, 2011, Beirut, Lebanon.
Prasad, A and Rajendra, S and Rajan, K and Govindarajan, R and Bondhugula, U (2022) Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. In: 55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, 1 October 2022 - 5 October 2022, Chicago, pp. 494-511.
Anantpur, Jayvant and Govindarajan, R (2017) Taming warp divergence. In: 2017 International Symposium on Code Generation and Optimization, CGO 2017, 4 - 8 February 2017, Austin, pp. 50-60.
Anantpur, Jayvant and Govindarajan, R (2013) Runtime dependence computation and execution of loops on heterogeneous systems. In: 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 23-27 Feb. 2013, Shenzhen, pp. 151-160.
Prabhakar, Raghu and Govindarajan , R and Thazhuthaveetil, Matthew J (2012) CUDA-for-clusters: a system for efficient execution of CUDA kernels on multi-core clusters. In: Proceedings of the 18th International Conference Euro-Par 2012, August 27-31, 2012, Rhodes Island, Greece.
Pai, Sreepathi and Govindarajan, R and Thazhuthaveetil , Matthew J (2012) Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. In: PACT '12 Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, 2012, New York, NY, USA.
Gulur, Nagendra Dwarakanath and Manikantan, R and Mehendale, Mahesh and Govindarajan, R (2012) Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. In: ICS '12 Proceedings of the 26th ACM International Conference on Supercomputing, 2012, New York, NY, USA.
Nasre, Rupesh and Govindarajan, R (2011) Prioritizing constraint evaluation for efficient points-to analysis. In: CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2011, IEEE Computer Society Washington, DC, USA.
Mannarswamy, Sandya and Govindarajan, R (2010) Analyzing Cache Performance Bottlenecks of STM Applications and addressing them with Compiler's help. In: 19th International Conference on Parallel Architectures and Compilation Techniques, SEP 11-15, 2010, Austrian Acad Sci Vienna, Vienna, AUSTRIA,, pp. 547-548.
Manikantan, R and Rajan, Kaushik and Govindarajan, R (2010) NUcache: A Multicore Cache Organization Based on Next-Use Distance. In: 19th International Conference on Parallel Architectures and Compilation Techniques, SEP 11-15, 2010, Austrian Acad Sci Vienna, Vienna, AUSTRIA, pp. 569-570.
Nasre, Rupesh and Rajan, Kaushik and Govindarajan, R and Khedker, Uday P (2009) Scalable Context-Sensitive Points-To Analysis Using Multi-Dimensional Bloom Filters. In: Seventh Asian Symposium on Programming Languages and Systems (APLAS 2009), Dec. 2009.
Girish, BC and Govindarajan, R (2009) Reducing Buffer Requirements in Core Routers using Dynamic Buffering. In: in Proc. of the 18th International Conference on Computer Communications and Networks (ICCCN 2009), Sept. 2009, San Francisco, CA.
Mannarswamy, Sandya and Govindarajan, R and Surendran, Rishi (2009) Region Based Structure Layout Optimization by Selective Data Copying. In: in Proc. of the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT-2009), Aug. 2009, Raleigh, NC.
Udupa, Abhishek and Govindarajan, R and Thazhuthaveetil, Matthew J (2009) Software Pipelined Execution of Stream Programs on GPUs. In: 7th International Symposium on Code Generation and Optimization, MAR 22-25, 2009, Seattle, WA, pp. 200-209.
Surendran, Sudhakar and Parekhji, Rubin and Govindarajan, R (2008) A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs. In: In Proc. of the 21st Annual IEEE SoC Conference, (SoCC-08), Newport Beach, CA, USA, 17-20 Sept. 2008 , Newport Beach, CA .
Kumar, Rajesh TS and Ravikumar, CP and Govindarajan, R (2008) Memory Architecture Exploration Framework for Cache Based Embedded SoC. In: Proc.of the International Conference on VLSI Design (VLSI-08) Hyderabad, India, 4-8 Jan. 2008, Hyderabad .
Thakur, Aditya and Govindarajan, R (2008) Comprehensive Path-sensitive Data-flow Analysis. In: 6th International Symposium on Code Generation and Optimization, APR 06-09,, Boston, pp. 55-63.
Girish, BC and Govindarajan, R (2008) Improving Performance of Result Caches in Network Processors. In: HiPC'08 Proceedings of the 15th international conference on High performance computing, Berlin, Heidelberg.
Gajjar, Mrugesh R and Govindarajan, R and Sreenivas, TV (2008) Online Unsupervised Pattern Discovery in Speech Using Parallelization. In: Proceedings of Interspeech 2008, September 22--26, 2008, Brisbane, Australia.
Pai, Sreepathi and Govindarajan, R and Thazhuthaveetil, MJ (2007) Limits of Data Level Parallelism. In: 14th Annual IEEE International Conference on High Performance Computing (HiPC), Goa, December 2007 (poster presentation), December 2007, Goa.
Govind, S and Govindarajan, R and Kuri, Joy (2007) Packet Reordering in Network Processors. In: IEEE International Parallel and Distributed Processing Symposium, 2007. IPDPS 2007., 26-30 March 2007 , Long Beach, CA.
Rajesh Kumar, TS and Ravikumar, CP and Govindarajan, R (2007) MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. In: inProc. of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC-07), Yokohama, Japan, 2007, 23-26 Jan. 2007 , Yokohama .
Rajesh Kumar, TS and Ravikumar, CP and Govindarajan, R (2007) MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. In: 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., Jan. 2007 , Bangalore.
Shyam, K and Govindarajan, R (2007) Compiler Directed Power Optimization for Partitioned Memory Architectures. In: Proc. of the Compiler Construction Conference (CC-07) Braga, Portugal, 2007., 2007, Portugal.
Shyam, K and Govindarajan, R (2007) Compiler-Directed Dynamic Voltage Scaling using Program Phases. In: HiPC'07 Proceedings of the 14th international conference on High performance computing, Heidelberg.
Girish, BC and Govindarajan, R (2007) A Petri net model for evaluating packet buffering strategies in a network processor. In: 4th International Conference on the Quantitative Evaluation of Systems, SEP 17-19, Edinburgh, SCOTLAND.
Nagarakatte, Santosh G and Govindarajan, R (2007) Register Allocation and Optimal Spill code Scheduling in Software Pipelined Loops using 0-1 Integer Linear Programming Formulation. In: CC'07 Proceedings of the 16th international conference on Compiler construction , Heidelberg.
Vivekanandham, Rajesh and Govindarajan, R (2007) A Scalable Low Power Store Queue For Large Instruction Window Superscalar processors. In: Poster session at the Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT-2007), September 15--19, 2007, Brasov, Romania.
Kumar, Santhosh V and Thazhuthaveetil, MJ and Govindarajan, R (2006) Exploiting Programmable Network Interfaces for Parallel Query Execution in Workstation Clusters. In: 20th International Parallel and Distributed Processing Symposium, 2006. IPDPS 2006., 25-29 April 2006, Rhodes Island.
Govind, S and Govindarajan, R (2006) Performance modeling and architecture exploration of network processors. In: Second International Conference on the Quantitative Evaluation of Systems, 2005., 19-22 Sept. 2005.
Vivekanandham, Rajesh and Amrutur, Bharadwaj and Govindarajan, R (2006) A Scalable Low Power Issue Queue for Large Instruction Window Processors. In: ICS '06 Proceedings of the 20th annual international conference on Supercomputing , June 2006, Cairns, Australia.
Rajan, Kaushik and Govindarajan, R (2006) Two-level Mapping Based Cache Index Selection for Packet Forwarding Engines. In: PACT '06 Proceedings of the 15th international conference on Parallel architectures and compilation techniques, Sept. 2006, New York, NY.
Yang, Hongbo and Govindarajan, R and Gao, Guang R and Hu, Ziang (2004) Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation. In: 16th International Workshop, LCPC, October 2-4, 2003, USA.
Govindarajan, R and Yang, H and Amaral, JN and Zhang, C and Gao, GR (2001) Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. In: 15th International Parallel and Distributed Processing Symposium. IPDPS 2001, 23-27 April, San Francisco,California, pp. 1-8.
Govindarajan, R and Zhang, C and Gao, GR (2000) Minimum register instruction scheduling: a new approach for dynamic instruction issue processors. In: Languages and Compilers for Parallel Computing, 4-6 Aug. 1999, La Jolla, CA, USA, pp. 70-84.
Govindarajan, R and Altman, Erik R and Gao, Guang R (2000) A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. In: IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2000, 10-12 July, Boston,Massachusetts, 329 -338.
Ramanan, VJ and Govindarajan, R (1999) Resource usage modelling for software pipelining. In: Proceedings of 6th International Conference on High Performance Computing (HiPC'99) - Mobile Computing for this Millenium, 17-20 Dec. 1999, Calcutta, India, pp. 111-119.
Janaki Ramanan, V and Govindarajan, R (1999) Resource usage models for instruction scheduling: two new models and a classification. In: Proceedings of the 13th Association for Computer Machinery International Conference on Supercomputing, 20-25 June 1999, Rhodes, Greece, pp. 417-424.
Govindarajan, R and Rao, Narasimha NSS and Altman, ER and Gao, Guang R (1998) An Enhanced Co-Scheduling Method using Reduced MS-State Diagrams. In: First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing 1998. 1998 IPPS/SPDP, 30 March-3 April, Orlando,Florida, 168 -175.
Valluri, Madhavi Gopal and Govindarajan, R (1998) Modulo-Variable Expansion Sensitive Scheduling. In: 5th International Conference On High Performance Computing, 1998. HIPC '98, 17-20 December, Chennai,India, 334 -341.
Govindarajan, R and Agarwal, A and Franklin, M and Gopinath, K and Kathail, V and Palem, K and Sarkar, V and Valero, M (1997) Has Exploitable ILP Reached a Point of Diminishing Returns? In: 4th International Conference on High-Performance Computing (HiPC 97), Dec 18-21, 1997, Bangalore, India.
Govindarajan, R and Suciu, F and Zuberek, WM (1997) Timed Petri Net Models of Multithreaded Multiprocessor Architectures. In: Seventh International Workshop on Petri Nets and Performance Models, 1997, 3-6 June, Saint Malo, 153 -162.
Govindarajan, R and Rengarajan, S (1996) Buffer Allocation in Regular Dataflow Networks: An Approach Based on Coloring Circular-Arc Graphs. In: 3rd International Conference on High Performance Computing, 1996, 19-22 December, Trivandrum,India, pp. 419-424.
Govindarajan, R and Altman, Erik R and Gao, Guang R (1996) Co-Scheduling Hardware and Software Pipelines. In: Second International Symposium on High-Performance Computer Architecture, 3-7 February 1996, San Jose, California, pp. 52-61.
Govindarajan, R and Altman, Erik R and Gao, Guang R (1996) A Framework for Resource-Constrained Rate-Optimal Software Pipelining. UNSPECIFIED.
Chajwa, R and Menon, N and Ramaswamy, S and Govindarajan, R (2020) Waves, Algebraic Growth, and Clumping in Sedimenting Disk Arrays. In: Physical Review X, 10 (4).
Jose, S and Brandt, L and Govindarajan, R (2020) Localisation of optimal perturbations in variable viscosity channel flow. In: International Journal of Heat and Fluid Flow, 85 .
Kong, Martin and Pop, Antoniu and Pouchet, Louis-Noel and Govindarajan, R and Cohen, Albert and Sadayappan, P (2014) Compiler/Runtime Framework for Dynamic Dataflow Parallelization of Tiled Programs. In: ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 11 (4).
Gajjar, Mrugesh R and Sreenivas, TV and Govindarajan, R (2013) Fast Likelihood Computation in Speech Recognition using Matrices. In: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 70 (2). pp. 219-234.
Kumar, Rajesh TS and Govindarajan, R and Ravikumar, CP (2012) On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip. In: ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 11 (1).
Prasad, Ashwin and Anantpur, Jayvant and Govindarajan, R (2011) Automatic Compilation of MATLAB Programs for Synergistic Execution on Heterogeneous Processors. In: ACM Sigplan Notices, 46 (6). pp. 152-163.
Udupa, Abhishek and Govindarajan, R and Thazhuthaveetil, Matthew J (2009) Synergistic Execution of Stream Programs on Multicores with Accelerators. In: ACM Sigplan Notices, 44 (7). pp. 99-108.
Kumar, Santhosh V and Nanjundiah, R and Thazhuthaveetil, MJ and Govindarajan, R (2008) Impact of message compression on the scalability of an atmospheric modeling application on clusters. In: Parallel Computing, 34 (1). pp. 1-16.
Khodade, Prashant and Prabhu, A and Chandra, Nagasuma and Raha, Soumyendu and Govindarajan, R (2007) Parallel implementation of AutoDock. In: Journal of Applied Crystallography, 40 (3). pp. 598-599.
Rong, Hongbo and Tang, Zhizhong and Govindarajan, R and Douillet, Alban and Gao, Guang R (2007) Single-Dimension Software Pipelining for Multidimensional Loops. In: ACM Transactions on Architecture and Code Optimization (TACO), 4 (1). pp. 1-44.
Pai, Rajani and Govindarajan, R (2007) FEADS: A Framework for Exploring the Application Design Space on Network Processors. In: International Journal of Parallel Programming, 35 (1). pp. 1-31.
Chandar, Subash and Mehendale, Mahesh and Govindarajan, R (2006) Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. In: Journal of VLSI Signal Processing Systems, 44 (3). pp. 245-267.
Kudlur, Manjunath and Govindarajan, R (2004) Performance analysis of methods that overcome false sharing effects in software DSMs. In: Journal of Parallel and Distributed Computing, 64 (8). pp. 887-907.
Manoj, NP and Manjunath, KV and Govindarajan, R (2004) CAS-DSM: A Compiler Assisted Software Distributed Shared Memory. In: International Journal of Parallel Programming, 32 (2). pp. 77-122.
Govindarajan, R and Yang, Hongbo and Amaral, JN and Zhang, Chihong and Gao, Guang R (2003) Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. In: IEEE Transactions on Computers, 52 (1). pp. 4-20.
Sarvani, VVNS and Govindarajan, R (2003) Unified instruction reordering and algebraic transformations for minimum cost offset. In: Lecture Notes in Computer Science, 2826 . pp. 270-284.
Govindarajan, R and Gao, Guang R and Desai, Palash (2002) Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks. In: Journal of VLSI Signal Processing, The, 31 (3). pp. 207-229.
Govindarajan, R and Altman, Erik R and Gao, Guang R (2002) A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. In: Design Automation for Embedded Systems, 6 (3). pp. 243-275.
Govindarajan, R and Sivasubramaniam, Anand (2001) Special Issue on Cluster and Network-Based Computing. In: Journal of Parallel and Distributed Computing, 61 (11). pp. 1507-1511.
Sreraman, N and Govindarajan, R (2000) A vectorizing Compiler for Multimedia Extensions. In: International Journal of Parallel Programming, 28 (4). pp. 363-400.
Altman, Erik R and Govindarajan, R and Gao, Guang R (1998) A unified framework for instruction scheduling and mapping for function units with structural hazards. In: Journal of Parallel and Distributed Computing, 49 (2). pp. 259-293.
Govindarajan, R and Narasimha, R (1997) A low-order theory for stability of non-parallel boundary layer flows. In: Proceedings Of The Royal Society Of London Series A-Mathematical Physical And Engineering Sciences, 453 (1967). pp. 2537-2549.
Govindarajan, R and Muralimanohar, B and Koteeswaran, A and Venugopalan, AT and Varalakshmi, P and Shaila, MS and Ramachandran, S (1996) Occurrence of rinderpest in European pigs in India. In: The Veterinary Record, 139 (19). 473-473 .
Govindarajan, R and Krishna Murty, AV and Vijayakumar, K and Raghuram, PV (1993) Finite element estimation of elastic interlaminar stresses in laminates. In: Composites Engineering, 3 (5). pp. 451-466.
Govindarajan, R and Kumar, R and Kumar, D and Patnaik, LM (1989) PROMIDS: A PROtotype multi-rIng data flow system for functional programming languages. In: Microprocessing and Microprogramming, 26 (3). pp. 161-173.
Patnaik, LM and Govindarajan, R and Ramadoss, NS (1986) Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer. In: IEEE Transactions on Computers, 35 (3). pp. 229-244.
Govindarajan, R and Gao, Guang R (2015) Author Rebuttal to Rocha et al. ``Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks''. In: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 81 (1). pp. 135-136.
Sarma, Radhika A and Govindarajan, R (2003) An efficient web cache replacement policy. In: Lecture Notes in Computer Science, 2913 . 12-22 .
Kumar, Vinodh R and Narayanan, Lakshmi B and Govindarajan, R (2002) Dynamic path profile aided recompilation in a JAVA just-in-time compiler. In: Lecture Notes in Computer Science, 2552 . pp. 495-505.
Govindarajan, R and Patnaik, LM (1990) Lenient Execution and Concurrent Execution of Re-entrant Routines: Efficient Implementation in Data Flow Systems. In: Computer Journal, The, 33 (2). pp. 185-187.
Rong, Hongbo and Gao, Guang R and Douillet, Alban and Govindarajan, R (2005) Methods and products for processing Loop Nests. Patent Number(s) WO 2005029318 A2. Patent Assignee(s) University of Delaware.
