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Book Chapter

Zhang, Chihong and Govindarajan, Ramaswamy and Ryan, Sean and Gao, Guang R (1999) Efficient State-Diagram Construction Methods for Software Pipelining. [Book Chapter]

Conference Paper

Yang, Hongbo and Govindarajan, R and Gao, Guang R and Hu, Ziang (2004) Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation. In: 16th International Workshop, LCPC, October 2-4, 2003, USA.

Govindarajan, R and Altman, Erik R and Gao, Guang R (2000) A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. In: IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2000, 10-12 July, Boston,Massachusetts, 329 -338.

Govindarajan, R and Rao, Narasimha NSS and Altman, ER and Gao, Guang R (1998) An Enhanced Co-Scheduling Method using Reduced MS-State Diagrams. In: First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing 1998. 1998 IPPS/SPDP, 30 March-3 April, Orlando,Florida, 168 -175.

Govindarajan, R and Altman, Erik R and Gao, Guang R (1996) Co-Scheduling Hardware and Software Pipelines. In: Second International Symposium on High-Performance Computer Architecture, 3-7 February 1996, San Jose, California, pp. 52-61.

Departmental Technical Report

Govindarajan, R and Altman, Erik R and Gao, Guang R (1996) A Framework for Resource-Constrained Rate-Optimal Software Pipelining. UNSPECIFIED.

Journal Article

Rong, Hongbo and Tang, Zhizhong and Govindarajan, R and Douillet, Alban and Gao, Guang R (2007) Single-Dimension Software Pipelining for Multidimensional Loops. In: ACM Transactions on Architecture and Code Optimization (TACO), 4 (1). pp. 1-44.

Govindarajan, R and Yang, Hongbo and Amaral, JN and Zhang, Chihong and Gao, Guang R (2003) Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. In: IEEE Transactions on Computers, 52 (1). pp. 4-20.

Govindarajan, R and Gao, Guang R and Desai, Palash (2002) Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks. In: Journal of VLSI Signal Processing, The, 31 (3). pp. 207-229.

Govindarajan, R and Altman, Erik R and Gao, Guang R (2002) A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. In: Design Automation for Embedded Systems, 6 (3). pp. 243-275.

Altman, Erik R and Govindarajan, R and Gao, Guang R (1998) A unified framework for instruction scheduling and mapping for function units with structural hazards. In: Journal of Parallel and Distributed Computing, 49 (2). pp. 259-293.

Editorials/Short Communications

Govindarajan, R and Gao, Guang R (2015) Author Rebuttal to Rocha et al. ``Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks''. In: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 81 (1). pp. 135-136.

Patent

Rong, Hongbo and Gao, Guang R and Douillet, Alban and Govindarajan, R (2005) Methods and products for processing Loop Nests. Patent Number(s) WO 2005029318 A2. Patent Assignee(s) University of Delaware.