Browse by Author

Conference Proceedings

Sharat, Kavya and Bandishte, Sumeet and Varghese, Kuruvilla and Bharadwaj, Amrutur (2017) A Custom Designed RISC-V ISA Compatible Processor for SoC. In: 21st International Symposium on VLSI Design and Test (VDAT), JUN 29-JUL 02, 2017, Indian Inst Technol Roorkee, Roorkee, INDIA, pp. 570-577.

Kumar, Saurabh and Shrikanth, V and Bharadwaj, Amrutur and Asokan, Sundarrajan and Bobji, MS (2016) Estimating needle-tissue interaction forces for hollow needles using Fiber Bragg Grating Sensors. In: Conference on Optical Fibers and Sensors for Medical Diagnostics and Treatment Applications XVI, FEB 13-14, 2016.

Conference Paper

Budi, Suseela and Gupta, Pradeep and Varghese, Kuruvilla and Bharadwaj, Amrutur (2018) A RISC-V ISA Compatible Processor IP for SoC. In: 2018 INTERNATIONAL SYMPOSIUM ON DEVICES, CIRCUITS AND SYSTEMS (ISDCS), MAR 29-31, 2018, Howrah, INDIA.

Viveka, KR and Bharadwaj , Amrutur (2013) Digitally controlled variation tolerant timing generation technique for SRAM sense amplifiers. In: 2013 5th Asia Symposium on Quality Electronic Design (ASQED), , 26-28 Aug. 2013 , Penang .

Das, Pratap Kumar and Bharadwaj, Amrutur and Sridhar, J and Visvanathan, V (2008) On-Chip Clock Network Skew Measurement using Sub-Sampling. In: 4th IEEE Asian Solid-State Circuits Conference, NOV 03-05, 2008, Fukuoka, Japan.

Gupte, Ajit and Bharadwaj, Amrutur (2008) An Adaptive Feature Based Low Power Motion Estimation Algorithm. In: IEEE International Conference on Multimedia & Expo, Hannover, Germany, June 23 2008-April 26 2008 , Hannover.

Vijay, UK and Bharadwaj, Amrutur (2007) Continous Time Sigma-Delta Modulator Employing a Novel Comparator Architecture. In: 20th International Conference on VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 6-10 Jan. 2007 , Bangalore.

Varadarajan, Keshavan and Nandy, SK and Sharda, Vishal and Bharadwaj, Amrutur and Iyer, Ravi and Makineni, Srihari and Newell, Donald (2006) Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. In: 39th Annual IEEE/ACM International Symposium on Microarchitecture,, Dec 09-13, 2006, Orlando, FL, pp. 433-442.

Journal Article

Janakiraman, V and Bharadwaj, Amrutur and Visvanathan, V (2010) Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29 (7). pp. 1056-1069.