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Srinivas, M and Patnaik, LM (1996) On generating optimal signal probabilities for random tests: A genetic approach. In: VLSI Design, 4 (3). pp. 207-215.
Majhi, AK and Jacob, J and Patnaik, LM (1996) A novel path delay fault simulator using binary logic. In: VLSI Design, 4 (3). pp. 167-179.
