Browse by IISc Authors

Conference Proceedings

Dey, Arnab and Jose, Sebin and Varghese, Kuruvilla and Srinivasa, Shayan Garani (2017) A High-throughput Clock-less Architecture for Soft-output Viterbi Detection. In: 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), AUG 06-09, 2017, Tufts Univ, Medford Somerville Campus, Boston, MA, pp. 779-782.

Sharat, Kavya and Bandishte, Sumeet and Varghese, Kuruvilla and Bharadwaj, Amrutur (2017) A Custom Designed RISC-V ISA Compatible Processor for SoC. In: 21st International Symposium on VLSI Design and Test (VDAT), JUN 29-JUL 02, 2017, Indian Inst Technol Roorkee, Roorkee, INDIA, pp. 570-577.

Datta, Saugata and Varghese, Kuruvilla and Srinivasa, Shayan Garani (2016) A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. In: 29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID), JAN 04-08, 2016, Kolkata, INDIA, pp. 439-444.

Devi, Anant and Gandhi, Maulik and Varghese, Kuruvilla and Gope, Dipanjan (2013) Hardware Accelerator for 3D Method of Moments based Parasitic Extraction. In: IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), DEC 12-15, 2013, Nara, JAPAN, pp. 100-103.

Conference Paper

Budi, Suseela and Gupta, Pradeep and Varghese, Kuruvilla and Bharadwaj, Amrutur (2018) A RISC-V ISA Compatible Processor IP for SoC. In: 2018 INTERNATIONAL SYMPOSIUM ON DEVICES, CIRCUITS AND SYSTEMS (ISDCS), MAR 29-31, 2018, Howrah, INDIA.

Shah, Jimit and Raghunandan, KS and Varghese, Kuruvilla (2012) HD resolution intra prediction architecture for H.264 decoder. In: 2012 25th International Conference on VLSI Design , January 07-January 11, Hyderabad.

Journal Article

Shah, Nimish and Chaudhari, Paragkumar and Varghese, Kuruvilla (2018) Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network. In: IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 29 (12). pp. 5922-5934.

Devi, Anant and Gandhi, Maulik and Varghese, Kuruvilla and Gope, Dipanjan (2016) Accelerating method of moments based package-board 3D parasitic extraction using FPGA. In: MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 58 (4). pp. 776-783.

Venkateshan, Sriram and Patel, Alap and Varghese, Kuruvilla (2015) Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23 (10). pp. 2221-2232.