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Design of Low Power Current-Mode Flash ADC

Bhat, MS and Rekha, S and Jamadagni, HS (2004) Design of Low Power Current-Mode Flash ADC. In: IEEE Region 10 Conference,TENCON 2004, 21-24 November, Chiang Mai, Thailand, Vol.4, 241-244.

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The design of a high-speed current-mode CMOS flash analog-to-digital converter (ADC) is presented. For high-speed operation, current mirroring technique with current comparison architecture is used and its advantages and limitations are explained. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance is investigated. A maximum sampling speed of 80Ms/sec is achieved at 78mW power consumption. The ADC is designed using $0.7-\mu{m}$ CMOS technolog.

Item Type: Conference Paper
Publisher: IEEE
Additional Information: Copyright 2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly Centre for Electronic Design & Technology)
Date Deposited: 22 Aug 2008
Last Modified: 19 Sep 2010 04:35
URI: http://eprints.iisc.ac.in/id/eprint/9947

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