Analysis of Control Flow Patterns in the Execution of SPEC CPU2000 Benchmark Programs

Joseph, PJ and Jacob, Matthew T (2003) Analysis of Control Flow Patterns in the Execution of SPEC CPU2000 Benchmark Programs. In: Conference on Convergent Technologies for the Asia-Pacific Region: IEEE TENCON 2003, 15-17 October, 2003, Bangalore, India, Vol.3 1143-1147.

Preview

PDF spec2000.pdf Download (463kB)

Abstract

Trace cache, an important building block in modem wide-issue processors, buffers and reuses dynamic instruction traces. The selection of relevant traces to the buffered is a critical factor in trace cache performance. The relevance of a trace, determined by its repetition count, is closely tied to the control flow behavior of programs. Hence, we analyse the control flow patterns in the SPEC CPU2000 benchmarks, We detect the loops in the CPU2000 integer benchmarks and study the loop path properties. The loop paths show wide vciation in sizes; sizes ranging from 8 to 100,000 instructions are observed for significant loop paths. In 6 of the 12 benchmarks, loop paths fit within typical L 1 cache sizes. We use the SEQUITUR algorithm to generate reasonably small sets of control flow paths that cover 99% of instruction execution in the benchmarks. These traces cover more than 95% of program execution with different inputs.

Item Type:	Conference Paper
Publisher:	IEEE
Additional Information:	©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre:	Division of Electrical Sciences > Computer Science & Automation
Date Deposited:	08 Jul 2004
Last Modified:	19 Sep 2010 04:13
URI:	http://eprints.iisc.ac.in/id/eprint/993

Actions (login required)

View Item